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benefits and features ? simplifies the design of a low - cost, universal rs - 2 32 com port to 1- wire ? interface true - ground o interface to an rs - 232 com port for reading and writing 1 - wire devices o works with bipolar as well as unipolar logic signals o sle w rate controlled 1 - wire pulldown and active pullup to accommodate long lines and reduce radiation o communicates at data rates of 9.6kbps (default), 19.2kbps, 57.6kbps, and 115.2kbps o self - calibrating time base with 5% tolerance for serial and 1 - wire commun ication o user - selectable rxd/txd polarity minimizes component count when interfacing to 5v based rs232 systems or directly to uarts o smart protocol combines data and control information without requiring extra pins o compatible with optical, ir, and rf to rs23 2 converters ? single product supports various ibutton ? or 1- wire device types for easy system integration o supports reading and writing at standard and overdrive speeds o provides strong pullup to 5v for temperature and eeprom 1 - wire devices o programs 1 - wire ep rom devices with external 12v power supply o programmable 1 - wire timing and driver characteristics accommodate a wide range of slave device configurations at standard speed o operates over 4.5v to 5.5v from - 40c to +85c pin assignment pin descri ption gnd - ground 1- w - 1- wire input/output nc - no connection v dd - 4.5v to 5.5v v pp - optional eprom programming voltage pol - rxd/txd polarity select txd - serial data from uart rxd - serial data to uart ordering information part temp range pin - package ds2480b+ - 40c to +85c 8 so ds2480b+t&r - 40c to +85c 8 so + denotes a lead(pb) - free/rohs - compliant package. t&r = tape and reel. description the ds2480b is a serial port to 1 - wire interface chip that supports standard and overd rive speeds. it con - nects directly to uarts and 5v rs232 systems. interfacing to rs232c (12v levels) requires a passive clamping circuit and one 5v to 12v level translator. internal timers relieve the host of the burden of generating the time - critical 1 - wire communication waveforms. in contrast to the ds9097(e) where a full character must be sent by the host for each 1 - wire time slot, the ds2480b can translate each character ds2480b serial to 1 - wire l ine driver 1 9 - 5047; 4 /1 5 1 2 3 4 8 7 6 5 gnd 1 - w nc vdd rxd txd pol vpp 8 - pin so (150 mil) 1 - wire and ibutton are registered trademarks of maxim integrated products, inc. ma xim integrated 1
ds2480b into eight 1 - wire time slots, thereby increasing the data throughput significantl y. in addition, the ds2480b can be set to communicate at four different data rates, including 115.2kbps, 57.6kbps, and 19.2kbps, with 9.6kbps being the power - on default. command codes received from the host?s crystal controlled uart serve as a reference to continuously calibrate the on - chip timing generator. the ds2480b uses a unique protocol that merges data and control information without requiring control pins. this approach maintains compatibility to off - the - shelf serial to wireless converters, allowing easy realization of 1 - wire media jumpers. the various control functions of the ds2480b are optimized for 1 - wire networks and support the special needs of all current 1 - wire devices including eprom - based add - only memories, eeprom devices, and 1 - wire thermo meters. see application note 192: using the ds2480b serial 1 - wire driver for detailed software examples. detailed pin description pin symbol description 1 gnd ground pin. common ground reference and ground return for 1 - wire bus 2 1- w 1 - wire input/output pin. no connection 4 v dd po wer input pin. power supply for the chip and 1 - wire pullup voltage, 5v 10%, must always be lower than or equal to v pp . v dd should be derived from v pp by a separate voltage regulator whenever possible. 5 v pp eprom programming voltage. 12v supply input fo r eprom programming. if eprom programming is not required, connect this pin directly to the system?s 5v supply. 6 pol rxd/txd polarity select. serial data from uart. serial data to uart. 12v rs232 systems an external level translator must be provided. overview the ds2480b directly interfaces a 5v serial communication port with its lines txd (transmit) and rxd (receive) to a 1 - wire bus. in addition the device performs a speed conversion allowing the data rate at the communication port to be different from the 1 - wire data rate. several parameters relating to the 1 - wire port and its timing as well as the communication speed at both the port and the 1 - wire bus are configurable. the circuit t o achieve these functions is outlined in the block diagram (see figure 1). the device gets its input data from the serial communication port of the host computer through pin txd. for compatibility with active - high as well as active - low systems, the incomi ng signal can be inverted by means of the polarity input pol. the polarity chosen by hard - wiring the logic level of this pin is also valid for the output pin rxd. if for minimizing the interface hardware an asymmetry between rxd and txd is desired, this ca n be achieved by setting the most significant bit of the speed control parameter to a 1 (see configuration parameter value codes ). with the ms bit of the speed control set to 1, the polarity at txd is still selected by the logic level at pol, but the polar ity at rxd will be the opposite of what the logic level at pol specifies. maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 2
ds2480b as data enters the core of the ds2480b?s logic circuitry, it is analyzed to separate data and command bytes and to calibrate the device?s timing generator. the timing generator cont rols all speed relations of the communication interface and the 1 - wire bus as well as the waveforms on the 1 - wire bus. command bytes either affect the configuration setting or generate certain waveforms on the 1 - wire bus. data bytes are simply translated by the protocol converter into the appropriate 1 - wire activities. each data byte generates a return byte from the 1 - wire bus that is communicated back to the host through the rxd pin as soon as the activity on the 1 - wire bus is completed. the 1 - wire drive r shapes the slopes of the 1 - wire waveforms, applies programming pulses or strong pullup to 5v and reads the 1 - wire bus using a non - ttl threshold to maximize the noise margin for best performance on large 1 - wire networks. figure 1 . ds2480b block diagram device operation the ds2480b can be described as a complex state machine with two static and several dynamic states. two device - internal flags as well as functions assigned to certain bit positions in the command codes determine the behavior of the chip, as shown in the state transition diagram (figure 2). the ds2480b requires and generates a communication protocol of 8 data bits per character, 1 stop bit and no parity. it is permissible to use 2 stop bits on the txd line. however, the ds2480b only assert s a single stop bit on rxd. when powering up, the ds2480b performs a master reset cycle and enters the command mode , which is one of the two static states. the device now expects to receive one 1 - wire reset command on the txd line sent by the host at a d ata rate of 9600bps (see communication commands section for details). this command byte is required solely for calibration of the baud rate timing generator the ds2480b and is not translated into any activity on the 1 - wire bus. after this first command byt e the device is ready to receive and execute any command as described later in this document. note: baud rate calibration is valid only for the v dd operating voltage at which calibration is performed. post - calibration changes in v dd by more than 5% may cau se calibration error to exceed 5%. the ds2480b requires a 1 - wire reset command sent by the host at a data rate of 9600bps for calibration. data rates of 115200bps or higher during calibration may put the ds2480b in an undefined state, requiring a power - do wn reset to restore normal operation. maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 3
ds2480b figure 2. state transition diagram legend: v binary value (type of write time slot) ss 1 - wire speed selection code p if logic 1, generates strong pullup to 5v immediately following the time slot t type of pulse; 0 = strong pullup (5v), 1 = programming pulse (12v) q 1 = arm strong pullup after every byte; 0 = disarm h search accelerator control; 1 = accelerator on, 0 = accelerator off zzz configuration parameter code (write), 000 = read configuration parameter vvv configuration parameter value code (write), configuration parameter code (read) x don?t care maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 4
ds2480b a master reset cycle can also be generated by means of software. this may be necessary if the host for any reason has lost synchronization with the device. the ds2480b will perform a master reset cycle equivalent to the power - on reset if it detects start polarity in place of the stop bit. the host has several options to generate this condition. these include making the uart generate a break signal, sending a nul l character at a data rate of 4800bps and sending any character with parity enabled and selecting space polarity for the parity bit. as with the power - on reset, the ds2480b requires a 1 - wire reset command sent by the host at a data rate of 9600bps for cali bration. after the ds2480b has reached the command mode, the host can send commands such as 1 - wire reset, pulse, configuration, search accelerator, and single bit functions or switch over to the second static state called data mode . in data mode the ds248 0b simply converts bytes it receives at the txd pin into their equivalent 1 - wire waveforms and reports the results back to the host through the rxd pin. if the search accelerator is on, each byte seen at txd will generate a 12 - bit sequence on the 1 - wire bu s (see search accelerator section for details). if the strong pullup to 5v is enabled (see pulse command ), each byte on the 1 - wire bus will be followed by a pause of predefined duration where the bus is pulled to 5v via a low - impedance transistor in the 1 - wire driver circuit. while being in the data mode the ds2480b checks each byte received from the host for the reserved code that is used to switch back to command mode. to be able to write any possible code (including the reserved one) to the 1 - wire bus, the transition to the command mode is as follows: after having received the code for switching to command mode, the device temporarily enters the check mode where it waits for the next byte. if both bytes are the same, the byte is sent once to the 1 - wire b us and the device returns to the data mode. if the second byte is different from the reserved code, it will be executed as command and the device finally enters the command mode. as a consequence, if the reserved code that normally switches to command mode is to be written to the 1 - wire bus, this code byte must be sent twice (duplicated). this detail must be considered carefully when developing software drivers for the ds2480b. after having completed a memory function with a device on the 1 - wire bus it is recommended to issue a reset pulse. this means that the ds2480b has to be switched to command mode. the host then sends the appropriate command code and continues performing other tasks. if during this time a device arrives at the 1 - wire bus it will genera te a presence pulse. the ds2480b will recognize this unsolicited presence pulse and notify the host by sending a byte such as xxxxxx01b. the xs represent undefined bit values. the fact that the host receives the byte unsolicited together with the pattern 0 1b in the least significant 2 bits marks the bus arrival. if the ds2480b is left in data mode after completing a memory function command it will not report any bus arrival to the host. command code overview the ds2480b is controlled by a variety of comman ds. all command codes are 8 bits long. the most significant bit of each command code distinguishes between communication and configuration commands. configuration commands access the configuration registers. they can write or read any of the configurable p arameters. communication commands use data of the configuration register in order to generate activity on the 1 - wire bus and/or (dis)arm the strong pullup after every byte or (de)activate the search accelerator without generating activity on the 1 - wire bus . details on the command codes are included in the state transition diagram (figure 2). a full explanation is given in the subsequent communication commands and configuration commands sections. maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 5
ds2480b in addition to the command codes explained in the subsequent sections the ds2480b understands the following reserved command codes: e1h switch to data mode e3h switch to command mode f1h pulse termination except for these reserved commands, the search accelerator control and the first byte after power - on reset or master reset cycle, every legal command byte generates a response byte. the pulse termination code triggers the response byte of the terminated pulse command. illegal command bytes do not generate a command response byte. communication commands the ds248 0b supports four communication function commands: reset, single bit, pulse, and search accelerator control. details on the assignment of each bit of the command codes are shown in table 1. the corresponding command response bytes are detailed in table 2. t he reset, search accelerator control and single bit commands include bits to select the 1 - wire communication speed (standard, flexible, overdrive). even if a command does not generate activity on the 1 - wire bus, these bits are latched inside the device and will take effect immediately. reset the reset command must be used to begin all 1 - wire communication. the speed selection included in the command code immediately takes effect. the response byte includes a code for the reaction on the 1- wire bus (bits 0 and 1) and a code for the chip revision (bits 2 to 4). single bit the single bit command is used to generate a single time slot on the 1 - wire bus at the speed indicated by bits 2 and 3. the type of the time slot (write - 0 or write - 1) is determined by the logic value of bit 4. a read data time slot is identical to the write - 1 time slot. bits 0 and 1 of the response byte transmitted by the ds2480b at the end of the time slot reveal the value found on the 1 - wire bus when reading. for a time slot without a s ubsequent strong pullup, bit 1 of the command must be set to 0. for a time slot immediately followed by a strong pullup bit 1 must be set to 1. as soon as the strong pullup is over, the device will send a second response byte, code efh (read 1) or ech (rea d 0), depending on the value found on the 1 - wire bus when reading. maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 6
ds2480b table 1. communication command codes function bit 7 bit 6 bit 5 bit 4 bit 3, bit 2 bit 1 bit 0 single bit 1 0 0 0 = write 0 1 = write 1 00 reg. speed 01 flex. speed 10 od. speed 11 reg. speed see text 1 search accelerator control 1 0 1 0 = accelerator off 1 = accelerator on see text 00 reg. speed 01 flex. speed 10 od. speed 11 reg. speed 0 1 reset 1 1 0 (don?t care) 00 reg. speed 01 flex. speed 10 od. speed 11 reg. speed 0 1 pulse 1 1 1 0 = 5v strong pullup 1 = 12v prog. pulse 11 pulse see text 1 table 2. communication command response function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 single bit 1 0 0 same as sent 1 - wire read back, both bits same value reset 1 1 x 0 1 1 00 = 1 - wire shorted 01 = presence pulse 10 = alarming presence pulse 11 = no presence pulse pulse 1 1 1 same as sent undefined x: this bit is reserved and undefined. in previous data sheet versions this bit was used to indicate that a programming voltage w as present. search accelerator control the search accelerator control command is used to set or reset the search accelerator control flag. bit 4 of the command code contains the state to which the accelerator control flag is to be set. if the flag is set to a 1 (on) the device translates every byte received in data mode into a 12 - bit sequence on the 1 - wire bus. for details on how the search accelerator works please refer to the section search accelerator operation. before activating the search accelerator, one must make sure that the strong pullup after every byte is disarmed (see pulse command ). the search accelerator command does not generate a command response byte. although the search accelerator control command itself does not generate any 1 - wire acti vity, it can be used to select the communication speed on the 1 - wire bus. the speed selection (if different from the previous setting, e.g., from a reset command) will take effect immediately. pulse the pulse command serves several functions that are sele cted by the contents of bit 1 and bit 4 of the command code. the main functions are generating a strong pullup to 5v and generating 12v programming pulses for eprom devices (if the 12v are available at the v pp pin). the secondary function maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 7
ds2480b of the pulse comm and is arming and disarming a strong pullup after every subsequent byte in data mode. the arm/disarm function is controlled by bit 1 of the command code. bit 4 determines whether the device will generate a strong pullup to 5v or a 12v programming pulse. th e table below summarizes these options. bit 4 bit 1 function 0 0 strong pullup to 5v and disarm 1 0 12v programming pulse and disarm 0 1 strong pullup to 5v and arm 1 1 12v programming pulse and arm the strong pullup to 5v is required to program eep rom devices or to operate special function devices that require a higher current for a limited time after having received a ?go and convert? command. therefore, and because it significantly reduces the effective data throughput on the 1 - wire bus, the stron g pullup is disarmed most of the time. although arming or disarming is simultaneously possible while generating a programming pulse, this is not recommended since it is likely to destroy the ds2480b if non- eprom devices are connected to the 1 - wire bus. th e duration of the strong pullup or programming pulse is determined by configuration parameters and ranges from a few microseconds up to unlimited (see configuration commands section). however, unlim ited duration is not allowed in conjunction with arming t he strong pullup after every byte. as long as the ds2480b is in command mode the host may termi nate a strong pullup or programming pulse prema turely at any time by sending the command code f1h. the response byte is generated as soon as the strong pullup or programming pulse is over (either because the predefined time has elapsed, the high current demand is over, or due to termination by the host). the response byte mainly returns the com mand code as sent by the host, but the 2 least significant bits are undefined. if the strong pullup is armed and the device is in data mode, the end of the strong pullup will be signaled as code f6h if the most significant bit of the preceding data byte on the 1 - wire bus is a 1 and 76h otherwise. the host will see this r esponse byte in addition to the response on the data byte sent (see also waveforms section later in this document). search accelerator introduction the search accelerator is a logic block inside the ds2480b that allows using the search rom function very e fficiently under modern operating systems. without the ds2480b all 1 - wire port adapters have to involve the computer?s cpu for every single time slot or pulse to be generated on the 1 - wire bus. under some operating systems it may take several milliseconds or more to get the first time slot generated on the 1 - wire bus when sending commands to the uart. every subsequent time slot will be generated in much less time, since the computer simply sends out ?streams? ? a long chain of bytes. this works reasonably we ll when reading or writing large blocks of data. searching the 1 - wire bus to identify all rom ids of the devices connected, however, requires reading 2 bits, making a decision and then writing a bit. this procedure is to be repeated 64 times to identify a nd address a single device. with the overhead of modern operating systems this fairly simple process takes a lot of time, reducing the discovery rate of devices on the 1 - wire bus. to solve this problem the search accelerator was developed. maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 8
ds2480b during the exec ution of the search rom function, the search accelerator receives from the host information on the preferred path to choose as one contiguous chain of bytes and then translates it into the appropriate time slots on the 1 - wire bus. in addition, the search a ccelerator reports back to the host the rom id of the device actually addressed and the bit positions in which conflicts were found. (if the rom id of one device has a 0 in a bit position where another device has a 1, this is called a ?conflict? on the ele ctrical level and ?discrepancy? on the logical level. see application note 187 for a more detailed discussion of the search rom.) this helps the host to select the preferred path for the next search rom activity. since the rom id of all 1 - wire/ibutton dev ices is 64 bits long and a conflict may occur in any of these bits, the total length of data reported to the host is 128 bits or 16 bytes. to avoid data overrun (if the cpu sends data faster than it can be processed) the protocol for the search accelerator operation was defined so that one has to send as many bytes as one will receive. this way the cpu sends 16 bytes for each path and the uart guarantees the correct data timing and frees the cpu for other tasks while the ds2480b performs a search rom functi on. search accelerator operation after the search accelerator is activated and the data mode is selected, the host must send 16 bytes to complete a single search rom pass on the 1 - wire bus. these bytes are constructed as follows: first byte 7 6 5 4 3 2 1 0 r 3 x 3 r 2 x 2 r 1 x 1 r 0 x 0 et cetera 16 th byte 7 6 5 4 3 2 1 0 r 63 x 63 r 62 x 62 r 61 x 61 r 60 x 60 in this scheme, the index (values from 0 to 63, ?n?) designates the position of the bit in the rom id of a 1- wire/ibutton device. the character ?x? marks b its that act as filler and do not require a specific value (?don?t care? bits). the character ?r? marks the path to go at that particular bit in case of a conflict during the execution of the rom search. for each bit position n (values from 0 to 63) the d s2480b will generate three time slots on the 1 - wire bus. these are referenced as: b0 for the first time slot (read data) b1 for the second time slot (read data) and b2 for the third time slot (write data). maxim integrated ................................ ................................ ................................ ................................ ................................ ............................. 9
ds2480b the type of time slot b2 (write 1 or write 0) is determined by the ds2480b as follows: b2 = r n if conflict (as chosen by the host) = b 0 if no conflict (there is no alternative) = 1 if error (there is no response) the response the host will receive during a complete pass through a search rom function us ing the search accelerator consists of 16 bytes as follows: first byte 7 6 5 4 3 2 1 0 r? 3 d 3 r? 2 d 2 r? 1 d 1 r? 0 d 0 et cetera 16 th byte 7 6 5 4 3 2 1 0 r? 63 d 63 r? 62 d 62 r? 61 d 61 r? 60 d 60 as before, the index (values from 0 to 63, ?n?) designates the position of the bit in the rom id of a 1- wire/ibutton device. the character ?d? marks the discrepancy flag in that particular bit position. the discrepancy flag will be 1 if there is a conflict, or no response in that particular bit position, and 0 otherw ise. the character ?r? marks the actually chosen path at that particular bit position. the chosen path is identical to b2 for the particular bit position of the rom id. to perform a search rom sequence one starts with all bits r n being 0s. in case of a bu s error, all subsequent response bits r? n are 1s until the search accelerator is deactivated. thus, if r? 63 and d 63 are both 1, an error has occurred during the search procedure and the last sequence has to be repeated. otherwise r? n (n = 0 ... 63) is the rom code of the device that has been found and addressed. for the next search rom sequence one reuses the previous set r n (n = 0 ... 63) but sets r m to 1 with ?m? being the index number of the highest discrepancy flag (that is, 1) and sets all r i to 0 wit h i > m. this process is repeated until the highest discrepancy occurs in the same bit position for two consecutive passes. the table below shows an example for the communication between host and ds2480b to perform one pass through the search rom function using the search accelerator. after a device has been identified and addressed, a memory function (not specified here) is executed and finally a reset pulse is generated. this example assumes that the ds2480b was in command mode and that standard 1 - wire s peed is used. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 10
ds2480b search accelerator usage example action sequence host tx host rx generate reset pulse c1 cd or ed set data mode e1 (nothing) search rom command f0 (as sent) set command mode e3 (nothing) search accelerator on b1 (nothing) set data mode e1 (nothing) send 16 bytes data (response) set command mode e3 (nothing) search accelerator off a1 (nothing) set data mode e1 (nothing) do memory function set command mode e3 (nothing) generate reset pulse c1 cd or ed configuration commands the ds2480b is designed to be configurable for the varying requirements of its application. when the device powers up and/or performs a master reset cycle, the hard - wired default configuration settings take effect. these settings will work on a short 1 - wire b us and assume standard 1 - wire communication speed. to change these default settings and to verify the current settings, the logic of the ds2480b supports configuration commands. a summary of the available configuration parameters, their default settings at standard and overdrive speed and their applicability is shown in table 3. parameters not related to the communication speed on the 1 - wire bus specify the duration of the 12v programming pulse, the duration of the strong pullup to 5v, and the baud rate on the interface that connects the ds2480b to the host. the remaining three parameters are used to modify the 1 - wire communication waveforms if one selects ?flexible speed? (see communication com mands for speed selection). flexible speed is implemented to improve the perfor mance of large 1 - wire networks. this is accomplished by: ? limiting the slew rate on falling edges (e. g., at the beginning of time slots, to reduce ringing), ? extending the write - 1 low time (allows the current flow through the network to end slowly, to prevent voltage spikes from inductive kickback), ? delaying the time point when reading a bit from the 1 - wire bus (gives the network more time to stabilize, to get a higher voltage margin) and ? adding extra recovery time between write - 0 time sl ots (allows more energy transfer through the network, to replenish the parasite power supply of the devices on the bus). the latter two functions are controlled by a single parameter. taking advantage of flexible speed requires changing one or more of the se parameters from their default values. otherwise the waveforms will be identical to those at standard speed. each configuration parameter is identified by its 3 - bit parameter code and can be programmed for one of a maximum eight different values using a 3- bit value code. a matrix of parameter codes and value codes with the associated physical values in shown in table 4. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 11
ds2480b table 3. configuration parameter overview parameter description configurable at default par. code standard flexible overdrive reg./ flex. overdrive pulldown slew rate control 001 15v/s 15v/s programming pulse duration 010 512s 512s strong pullup duration 011 3s 3 s 1s 3s rs232 baud rate 111 controlled edges section . for the parameters 010 (programming pulse duration) and 011 (strong pullup duration) one may select indefinite duration. this value, however, should only be selected if one is not going to switch the device to data mode. as long as the device stays in command mode, any pulse function (programming or strong pullup) that uses one of these parameters can be terminated by sending the command code f1h. termination is not possible if the device is in data mode. parameter 111 (rs232 baud rate) has two functions. it selects the baud rate and allows inversion of the signal at the rxd pin. using one of the value codes 100 to 111 will set the polarity at rxd to the opposite of what is defi ned by the logic level at the pol pin (asymmetry bit, see figure 1). this may reduce the component count in some applications of the device. note that when changing the baud rate, the ds2480b will send the command response byte at the new data rate. a sho rt explanation on the use of parameters 100 (write - 1 low time) and 101 (data sample offset/write - 0 recovery time) is given in the timing diagrams section later in this document. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 12
ds2480b table 4. configuration parameter value codes value codes parameter code 0 00 001 010 011 100 101 110 111 unit 001 (pdsrc) 15 2.2 1.65 1.37 1.1 0.83 0.7 0.55 v/s 010 (ppd) 32 64 128 256 512 1024 2048 s 011 (spud) 16.4 65.5 131 262 524 1048 note ms 100 (w1lt) 8 9 10 11 12 13 14 15 s 101 (dso/w0rt) 3 4 5 6 7 8 9 10 s 110 (load) 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 ma 111 (rbr) 9.6 19.2 57.6 115.2 9.6 19.2 57.6 115.2 kbps note : the value code 110 of parameter 011 (strong pullup duration) must not be used since it could cause unexpected results. the syntax of configuratio n commands is very simple. each 8 - bit code word contains a 3 - bit parameter code to specify the parameter and the 3 - bit value code to be selected. bit 7 of the command code is set to 0 and bit 0 is always a 1. to read the value code of a parameter, one writ es all 0s for the parameter code and puts the parameter code in place of the parameter value code. table 5 shows the details. the configuration command response byte is similar to the command byte itself. bit 0 of the response byte is always 0. when writi ng a parameter, the upper 7 bits are the echo of the command code. when reading a parameter, the current value code is returned in bit positions 1 to 3 with the upper 4 bits being the same as sent (see table 6). table 5. configuration command codes funct ion bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write parameter 0 parameter code parameter value code 1 read parameter 0 0 0 0 parameter code 1 table 6. configuration command response byte function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write parameter 0 same as sent same as sent 0 read parameter 0 same as sent parameter value code 0 maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 13
ds2480b controlled edges one of the tasks of the ds2480b is to actively shape the edges of the 1 - wire communication waveforms. this speeds up the recharging of th e 1 - wire bus (rising edges) and reduces ringing of long lines (falling edges). the circuitry for shaping rising edges is always on. the slew rate of falling edges is actively controlled only at flexible speed and requires the parameter for slew rate contro l being different from its power - on default value. all rising edges the active pullup of the rising edges reduces the rise time on the 1 - wire bus significantly compared to a simple resistive pullup. figure 4 shows how the ds2480b is involved in shaping a rising edge. figure 4 . active pullup the circuit operates as follows: at t 1 the pulldown (induced by the ds2480b or a device on the bus) ends. from this point on the 1 - wire bus is pulled high by the weak pullup current i weakpu provided by the ds2480b. the slope is determined by the load on the bus and the value of the pullup current. at t 2 the voltage crosses the threshold voltage v iapo . now the ds2480b switches over from the weak pullup current i weakpu to the higher current i actpu . as a consequence, th e voltage on the bus now rises faster. as the voltage on the bus crosses the threshold v iapto at t 3 , a timer is started. as long as this timer is on (t apuot ), the i actpu current will continue to flow. after the timer is expired, the ds2480b will switch bac k to the weak pullup current. excessive noise on the 1 - wire line at the v iapto level can cause an undesirable trip of the active pullup. external r - c filtering as discussed in the hardware application examples section and application note 148 should be use d to prevent false triggering. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 14
ds2480b falling edges (ds2480b - initiated) whenever the ds2480b begins pulling the 1 - wire bus low to initiate a time slot, for example, it first turns off the weak pullup current i weakpu . then, at standard and overdrive speeds it wil l generate a falling edge at a slew rate of typically 15v/ s. this value is acceptable for short 1 - wire busses and adequate for communication at overdrive speed. for 1 - wire networks of more than roughly 30m length one should always use flexible speed. one of the parameters that is adjustable at flexible speed is the slew rate of ds2480b - initiated falling edges. the effect of the slew rate control is shown in figure 5. figure 5 . slew rate control as extensive tests have shown, 1 - wire networks at a length of up to 300m will perform best if the fall time t f is in the range of 4 0.5 s. this translates into a slew rate of approximately 1v/ s. this slew rate is typically achieved by setting the configuration parameter 001 (pulldown slew rate control) to a value of 100 (see table 4). if the actual measured fall time is longer than the target value, one should use a value code of 011 or lower. if the fall time is shorter, one should use a value code of 101 or higher. once determined, the value code for the pulldown slew rate control parameter should be stored in the host and always be loaded into the ds2480b after a power - on or master reset cycle. timing diagrams this section explains the waveforms generated by the ds2480b on the 1 - wire bus in detail. first the communication waveforms such as the reset/presence detect sequence and t he time slots are discussed. after that follows a detailed description of the pulse function under various conditions. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 15
ds2480b 1- wire communication waveforms one of the major features of the ds2480b is that it relieves the host from generating the timing of the 1- wire signals and sampling the 1 - wire bus at the appropriate times. how this is done for the reset/presence detect sequence is shown in figure 6a. this sequence is composed of four timing segments: the reset low time t rstl , the short/interrupt sampling o ffset t si , the presence detect sampling offset t pdt and a delay time t fill . the timing segments t si , t pdt and t fill comprise the reset high time t rsth where 1 - wire slave devices assert their presence or interrupt pulse. during this time the ds2480b pulls t he 1 - wire bus high with its weak pullup current. the values of all timing segments for all 1 - wire speed options are shown in the table. since the reset/presence sequence is slow compared to the time slots, the values for standard and flexible speed are th e same. except for the falling edge of the presence pulse all edges are controlled by the ds2480b. the shape of the uncontrolled falling edge is determined by the capacitance of the 1 - wire bus and the number, speed and sink capability of the slave devices connected. figure 6a. reset/presence detect speed t rstl t si t pdt t fill t rsth standard 512s 8s 64s 512s 584s overdrive 64s 2s 8s 64s 74s flexible 512s 8s 64s 512s 584s after having received the command code for generating a reset/pre sence sequence, the ds2480b pulls the 1 - wire bus low for t rstl and then lets it go back to 5v. the ds2480b will now wait for the short/interrupt sampling offset t si to expire and then test the voltage on the 1 - wire bus to determine if there is a short or a n interrupt signal. if there is no short or interrupt (as shown in the picture), the ds2480b will wait for t pdt and test the voltage on the 1 - wire bus for a presence pulse. regardless of the result of the presence test, the ds2480b will then wait for t fill to expire and then send the command response byte to the host. if the test for interrupt or short reveals a logic 0, the ds2480b will wait for 4096 s and then test the 1- wire bus again. if a logic 0 is detected, the 1 - wire bus is shorted and a command r esponse byte with the code for short will be sent immediately. if a logic 1 is detected, the device will wait for t fill to expire, after which it will send the command response byte with the code for an alarming presence pulse. no additional testing for a presence pulse will be done. the ds2480b will perform the short/interrupt testing as described also at overdrive speed, although interrupt signaling is only defined for standard speed. the idle time following the reset/presence detect sequence depends on the serial communication speed and the host?s response time. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 16
ds2480b a write - 1 and read data time slot is comprised of the segments t low1 , t dso and t high . during write - 1 time slots, after the write - 1 low time t low1 is over, the ds2480b waits for the duration of th e data sample offset and then samples the voltage at the 1 - wire bus to read the response. after this, the waiting time t high1 must expire before the time slot is complete. a write - 0 time slot only consists of the two segments t low0 and t rec0 . if the netwo rk is large or heavily loaded, one should select flexible speed and extend t low1 to more than 8 s to allow the 1 - wire bus to completely discharge. since a large or heavily loaded network needs more time to recharge, it is also recommended to delay sampling the bus for reading. a higher value for t dso will increase the voltage margin and also provide extra energy to the slave devices when generating a long series of write 0 time slots. however, the total of t low1 + t dso should not exceed 22 s*. otherwise the slave device responding may have stopped pulling the bus low when transmitting a logic 0. the idle time between time slots within a byte or during a 12 - bit sequence while the search accelerator is on is 0. between bytes, 12 - bit search sequences and singl e bits the idle time depends on the rs232 data rate and the host?s response time. the response byte is sent to the host as soon as the last time slot of a byte, 12 - bit sequence or the command is completed. figure 6b. write - 1 and read data time slot spe ed t low1 t dso t high1 t slot * standard 8s 3s 49s 60s overdrive 1s 1s 8s 10s flexible 8s to 15s 3s to 10s 49s 60s to 74s figure 6c. write - 0 time slot speed t low0 t rec0 t slot * standard 57s 3s 60s overdrive 7s 3s 10s flexible 57 s 3s to 10s 60s to 67s *in a 5v environment ( 1v, full temperature range) the tolerance of the internal time base of 1 - wire slave devices is much narrower than what it is when operated at the minimum voltage of 2.8v. therefore, the timing generated by the ds2480b is in compliance with the requirement s of all 1 - wire/ibutton 1 - wire devices. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 17
ds2480b pulse waveforms, disarmed the pulse command can be used to generate a strong pullup to 5v and a 12v programming pulse, respectively. the duration of the pulse is predefined if the parameter value code of parameter 01 0 (programming pulse duration) has a value from 000 to 110, and parameter 011 (strong pullup duration) has a value from 000 to 101 (see table 4). figures 7a and 7b show the timing of a pulse with predefined duration, which should be considered the normal c ase. if infinite duration is chosen (parameter value code 111), the host must terminate the pulse command, as shown in figures 7c and 7d. all versions of figure 7 assume that bit 1 of the pulse command is 0, i.e., disarmed mode. see the communication com m ands: pulse section for more details on possibilities of the pulse command. figure 7a. strong pullup to 5v, predefined duration the processing of a pulse command is essentially the same, regardless if a strong pullup or a programming pulse is requested . at t 1 the host starts sending the pulse command byte. at t 2 the ds2480b has received the command and immediately generates the pulse. the pulse ends at t 3 and the ds2480b sends out the command response byte to inform the host that the command is complete d. the idle time between t 1 and t 2 is determined by the time to transmit the command byte at the selected baud rate. the idle time between t 3 and t 4 is comprised of the time to transmit the response byte, plus the response time of the host plus the time to transmit the command and/or data to generate the next time slot. figure 7b. 12v programming pulse, predefined duration a correct programming pulse can only be generated if the 12v programming voltage is available at the v pp pin of the ds2480b. the ris ing and falling edges of the programming pulse are actively controlled by ds2480b. the slew rate is approximately 14v/s and meets the requirements of 1 - wire eprom devices. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 18
ds2480b for eprom programming, only a single slave device should be connected to the 1 - wir e bus and the cable must to be short, not to exceed a few meters. one should not attempt generating a programming pulse with a non- eprom device on the bus; this may damage the device as well as the ds2480b. certain applications may require a duration for a strong pullup or programming pulse that cannot be realized using one of the predefined values. selecting infinite duration allows the host to generate pulses of any length. as a consequence, however, the host becomes responsible to actively control the d uration of the pulse. failing to do so may require a power - on reset or master reset cycle of the ds2480b. for this reason, infinite duration should only be used if absolutely necessary. the time to end a pulse of infinite duration strongly depends on the baud rate of the communication between host and ds2480b. neglecting the response time of the host, the minimum pulse durations are: 86.8s at 115.2kbps, 173.6s at 57.6kbps, 520s at 19.2kbps, and 1.04ms at 9.6kbps. figure 7c. strong pullup to 5v, infinit e duration as before, processing the command is essentially the same, regardless if it is for a strong pullup or a programming pulse. at t 1 the host starts sending the pulse command byte. at t 2 the ds2480b has received the command and immediately activa tes the strong pullup or switches in the 12v programming voltage. to end the pulse, the ds2480b must receive a termination command, code f1h, which occurs at t 3 . the termination command does not generate a response byte. the ds2480b will immediately end th e pulse and send out the response byte of the pulse command. the idle time between t 1 and t 2 is determined by the time to transmit the command byte at the selected baud rate. the idle time between t 3 and t 4 is comprised of the time to transmit the pulse re sponse byte, plus the response time of the host plus the time to transmit the command and/or data to generate the next time slot. figure 7d. 12v programming pulse, infinite duration maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 19
ds2480b pulse waveform, armed as explained in the communication commands secti on, bit 1 of the pulse command allows the arming of a strong pullup to 5v if the bit is set to 1. if the strong pullup is armed and the device is switched to data mode, there will be a strong pullup immediately following every byte on the 1 - wire bus. this mode is implemented to provide extra energy when writing to eeprom devices or to do a temperature conversion with the ds1920 temperature i button, for example. these devices need a strong pullup immediately after the power - consuming activity has been initia ted by a command code. to arm the strong pullup, one usually generates a ?dummy? pulse with bit 1 being 1 while the device is in command mode. to save time, the dummy pulse may immediately be terminated by sending the termination command, code f1h. then o ne switches to data mode and sends a command code that makes one or more slaves on the 1 - wire bus require extra energy. after the command execution is finished, one switches back to command mode and disarms the strong pullup by generating another dummy pul se. a complete temperature conversion sequence that shows the use of the armed pulse is included in the software driver examples section . figure 8. strong pullup to 5v, armed, predefined duration figures 8 shows the timing of the strong pullup in data mode. at t 1 the 8 th time slot of the byte sent to the 1- wire bus is completed. without any delay the ds2480b now activates the strong pullup and simultaneously starts sending the data response byte to the host. at t 2 the strong pullup ends and the ds2480b sends a pulse response byte to the host. the idle time between t 2 and t 3 is comprised of the time to transmit the pulse response byte, plus the response time of the host plus the time to transmit the command and/or data to generate the next time slot. sin ce in data mode the pulse termination command is not applicable, the duration of the strong pullup must be limited. see table 4, parameter 011 (strong pullup duration) for details. infinite duration, if accidentally selected, will require a power - on or ma ster reset cycle to get the ds2480b back to communicating with the host. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 20
ds2480b single bit with strong pullup similar to the pulse command, the single bit command also allows generating a strong pullup immediately following a time slot. the strong pullup of the single bit command, however, is controlled directly by bit 1 of the command code and therefore needs not be armed. since the ds2480b remains in command mode when using the single bit command, any duration of the strong pullup including infinite may be sele cted. figure 9a. single bit with strong pullup, predefined duration figure 9 shows the timing of the single bit command immediately following strong pullup. for predefined duration (figure 9a) the timing is as follows: at t 1 the time slot is completed. now the ds2480b activates the strong pullup and simultaneously starts sending the response byte of the single bit command to the host. at t 2 the strong pullup ends and the ds2480b sends out a pulse response byte. the idle time between t 2 and t 3 is compris ed of the time to transmit the pulse response byte, plus the response time of the host plus the time to transmit the command and/or data to generate the next time slot. figure 9b. single bit with strong pullup, infinite duration for infinite duration ( figure 9b) the strong pullup also begins immediately after the time slot is completed. to end the strong pullup, the ds2480b must receive a termination command, code f1h, which occurs at t 2 . the termination command does not generate a response byte. the ds 2480b will then immediately end the strong pullup and send out a pulse response byte. everything else is the same as with predefined duration. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 21
ds2480b the minimum duration of a strong pullup of infinite duration strongly depends on the baud rate of the communicat ion between host and ds2480b. the host must first receive the response byte of the single bit command, react to it and then transmit the termination command. neglecting the host?s response time, the shortest duration of an infinite strong pullup therefore is 173.6 s at 115.2kbps, 347.2 s at 57.6kbps, 1.04ms at 19.2kbps, and 2.08ms at 9.6kbps. software driver examples the ds2480b requires a software driver that translates the activities to be generated on the 1 - wire bus into the appropriate commands. the ex amples below cover typical situations, such as reading the rom, writing to the scratchpad of a memory i button, reading the memory of a memory i button, programming an add - only i button eprom and performing a temperature conversion with the ds1920 temperature i button. an example for the use of the search accelerator is included in the search accelerator section found earlier in this document. the ds2480b command codes used in these examples are valid for standard speed and will work properly on short 1 - wire b uses (<10m). the response byte on the reset command assumes a normal presence pulse, no alarm or short. the ds2480b includes a 1 - byte buffer that stores a byte received from the host while the previous byte is being translated into activity on the 1 - wire bus. for this reason the host may send another byte even without having received the response byte. sending bytes faster than they can be translated into 1 - wire activities may result in loss of data and/or synchronization and therefore should be avoided. read rom sequence action sequence host tx host rx generate reset pulse c1 cd or ed set data mode e1 (nothing) read rom command 33 (as sent) read rom id (8 bytes) ff (x8) rom id set command mode e3 (nothing) generate reset pulse c1 cd or ed write sc ratchpad sequence write 2 bytes to scratchpad at memory locations 16h and 17h action sequence host tx host rx generate reset pulse c1 cd or ed set data mode e1 (nothing) skip rom command cc cc write scratchpad command 0f (as sent) starting address ta1 16 (as sent) starting address ta2 00 (as sent) write to the scratchpad (2 bytes) (as sent) set command mode e3 (nothing) generate reset pulse c1 cd or ed maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 22
ds2480b read memory sequence action sequence host tx host rx generate reset pulse c1 cd or ed set dat a mode e1 (nothing) skip rom command cc cc read memory command f0 (as sent) starting address ta1 40 (as sent) starting address ta2 00 (as sent) read 8 bytes of data ff (x8) (data) set command mode e3 (nothing) generate reset pulse c1 cd or ed writ e eprom sequence (ds2505) write memory starting at address 40h action sequence host tx host rx set vpp dur. = 512s 29 28 generate reset pulse c1 cd or ed set data mode e1 (nothing) skip rom command cc (as sent) write memory command 0f (as sent) star ting address ta1 40 (as sent) starting address ta2 00 (as sent) *** send data byte (data) (as sent) receive crc16 ff (x2) crc16 set command mode e3 (nothing) generate program pulse fd response set data mode e1 (nothing) read written byte ff (data) go to *** to write the next byte or end the sequence as shown below set command mode e3 (nothing) generate reset pulse c1 cd or ed temperature conversion sequence action sequence host tx host rx set pullup dur. = 524ms 39 38 generate reset pulse c1 c d or ed set data mode e1 (nothing) skip rom command cc (as sent) set command mode e3 (nothing) arm strong pullup ef (nothing) terminate pulse f1 response set data mode e1 (nothing) convert temperature 44 (as sent) wait for pulse response (nothing) response set command mode e3 (nothing) disarm strong pullup ed (nothing) terminate pulse f1 response generate reset pulse c1 cd or ed maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 23
ds2480b hardware application examples this section discusses five typical application scenarios. the ds2480b can be configure d for eprom programming as well as for 5v operation only. output filtering as described in the controlled edges section, the ds2480b employs an active pullup on the rising edges of the 1 - wire waveform. excessive noise on the 1 - wire line in the region of the pullup trip voltage, v iapto, can cause an undesirable trip of the active pullup, which can disrupt 1 - wire communication. external r - c filtering as shown in figure 10 should be added to all ds2480b configurations with the exception of those that perfor m eprom programming. for eprom programming configurations the r - c filter cannot be used due to the voltage drop that will develop across the 100 resistor during programming. figure 10. r - c filtering 1 - wire bus return 5 v 5v operation only gnd 1 - w pol vdd vpp rxd txd ds2480b 470 pf see application note 148 for additional information. 62 ohms ds9503 to protect the 1 - wire port of the ds2480b from electrostatic discharge it is recommended to use a low - capacitance esd protection diode, such as the ds950x devices. fo r 5v operation a single device is sufficient. for eprom programming two ds950x devices must be connected in series to achieve a high enough breakdown voltage. figures 11a - c are examples of connecting the ds2480b directly to a uart or rs232c interface. the circuit becomes more complex if a 1 - wire bus is to be interfaced to a port that provides and expects inverted signals, but does not necessarily meet the rs232c ( r 12v) standard (figure 11b). maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 24
ds2480b figure 11a. uart direct sin (rxd) sout (txd) uart or c start stop 1 0 l m 1 - wire bus return 12 v gnd 1 - w pol vdd vpp rxd txd ds2480b 5v regulator 5 v * only one ds950x es d protection device with 5v with eprom programming 5v operation only gnd 1 - w pol vdd vpp rxd txd ds2480b * 470 pf 62 ohms optional filter ds9503 ds9503 ds9503 figure 11b. 5v rs232 sin (rxd) sout (txd) uart or c start stop 1 0 l m 1 - wire bus return dtr power stealing gnd 1 - w pol vpp vdd rxd txd ds2480b 62 ohms optional filter rts see text 22 f 0.1 f ds9503 470 pf the signals dtr and rts provide the power to operate the ds2480b. the resistor in the txd line and the schottky di ode limit the negative voltage at the txd pin of the ds2480b to 0.3v maximum. the resistor is typically 4.7k ? . if the inverting driver is current - limited to 1ma the resistor is not required. from the ds2480b?s perspective, this circuit will work with inve rted signals of 5v as well as 0 to 5v. depending on the voltage levels the host expects, it may be necessary to generate a negative voltage on the rxd line. figure 11c shows how this can be accomplished for a true rs232c system. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 25
ds2480b figure 11c. 12v rs232 sin (rxd) sout (txd) uart or c start stop 1 0 l m 1 - wire bus return dtr power stealing gnd 1 - w pol vpp vdd rxd txd ds2480b rts see text 2.7k 4.7v 5v regulator 6.8k 1 f bss110 s d +12vdc programming * * only one ds950x esd protection device with 5v ds9503 ds9503 in the interface to a true rs232c system ( 12v, figure 11c) the power for the ds2480b is stolen from dtr and rts. the software must make sure that at least one of these signals constantly provides the 12v operating voltage. th e 6.8k ? resistor and the 4.7v zener diode in the txd line limit the positive voltage at the txd pin of the ds2480b. the schottky diode limits the negative voltage to 0.3v maximum. the schottky diode in series with capacitor forms a parasitic supply to gene rate the negative bias for the host?s receive channel. the positive signal is switched in through the p - channel mosfet that connects to the rxd output of the ds2480b. in this circuit diagram the mosfet switches the rxd line to +5v, which normally is suffic ient for rs232c systems. switching to 12v is also possible, but requires a p - channel transistor with a different threshold voltage. the signal inversion caused by the transistor is compensated through the ds2480b by using a value code of 100, 101, 110, or 111 for the rs232 baud rate setting. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 26
ds2480b figure 11d. uart direct opto - isolated return sin (rxd) sout (txd) uart or c start stop 1 0 l m 5 v dc to dc converter * 1 - wire bus gnd 1 - w pol vdd vpp rxd txd ds2480b * only one ds950x esd protection device with 5v 5v 12 v hcpl - 2300 2.7k 5.1k 2.7k 5.1k ds9503 ds9503 the circuit in figure 11d is essentially the same as in figure 11a. the main difference is the opto - isolation. the characteristics of the opto - isol ators are not very critical. using a different type will affect the values of the resistors that limit the current through the leds and bias the photo transistors. figure 11e. 5 to 12v rs232 opto - isolated sin (rxd) sout (txd) uart or c start stop 1 0 l m 1 - wire bus return dtr power stealing gnd 1 - w pol vpp vdd rxd txd ds2480b rts 2.7k hcpl - 2300 5v regulator 1.5 k 1 f hcpl - 2202 5v +12vdc programming * * only one ds950x esd protection device with 5v 1.5k dc/dc convert. ds9503 ds9503 the circuit in fi gure 11e combines the true rs232c interface with opto - isolation. the energy to power the led in the txd channel and to provide the positive voltage for the host?s rxd input is stolen from dtr and rts. the negative voltage for the rxd input is taken from th e txd line through a parasitic supply consisting of a schottky diode in series with a capacitor. the hcpl - 2202 opto - isolator has a totem pole output that allows switching in positive as well as negative voltage. the +5v are sufficient for most rs232c syste ms. switching in 12v requires an opto - isolator with different voltage characteristics. in the schematic the hcpl - 2202 opto - isolator is sourced by the rxd pin of the ds2480b. it can as well be connected the traditional way where the ds2480b sinks the curre nt through the led. this, however, causes a signal inversion that has to be compensated through the ds2480b by using a value code of 100, 101, 110, or 111 for the rs232 baud rate setting. using other types of opto - isolators than shown in the schematic will at least require changing the values of the resistors. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 27
ds2480b figure 12 . rs232 data timing rxd line figure 13 . receive delay timing figure 14 . rs232 data timing txd line figure 15 . txd line asymmetry maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 28
ds2480b table 7. function and speed matrix baud rate 1 - wire speed function standard flexible overdrive 9600bps t idlet is guaranteed by the uart; no precautions necessary. x not recommended unless t idlet is controlled by the host through a wait function. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 29
ds2480b absolute maximum ratings* voltage on 1 - w to ground - 0.5v to +14.0v voltage on vpp to ground - 0.5v to +12.5v voltage on vdd, rxd, txd, pol to ground - 0.5v to +7.0v operating temperature range - 40c to +85c storage temperature range - 55 c to +125c lead temperature (soldering, 10s) +300 c soldering temperature (reflow) +260 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v dd = 4.5v to 5.5v; - 40c to +85c) parameter symbol min typ max units notes supply voltage v dd 4.5 5.0 5.5 v programming voltage v pp 12.0 12.25 v 1 operating current i dd 3.0 5.0 ma idle current on v pp i pp 20 $ 2 active pullup timer threshold v iapto v dd - 1.4 v dd - 1.1 v active pullup on threshold v iapo 0.95 1.2 v 15 1 - wire input high v ih1 3.4 v 1 - wire input low v il1 1.8 v txd/pol input resistor r i 30 n 3 txd/pol input levels v ih 2.7 v tx d/pol input levels v il 0.8 v 1 - wire weak pullup current i weakpu 1.5 3.0 5.4 ma 15 1 - wire active pullup current i actpu 7 15 ma strong pullup voltage drop @ 10ma load on 1 - w ? v strpu 0.6 v 4 programming voltage drop @ 10ma load on 1 - w ? v prog 0.30 v 5 rxd sink current @ 0.4v i olr 6 ma rxd source current @ v dd - 0.4v i ohr - 4 ma power on reset trip point v por 3.3 v capacitances (t a = 25c) parameter symbol min typ max units notes txd/pol input capacitance c in 5 pf 17 1 - wire input capa citance c in1 10 pf 17 maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 30
ds2480b ac electrical characteristics (v dd = 4.5v to 5.5v; - 40c to +85c) parameter symbol min typ max units notes uart bit time t t 8.68 104 s 6 device bit time t r 8.68 104 s 6, 7, 16 fall time rxd t fr 8 20 ns 8,17 rise t ime rxd t rr 13 27 ns 8,17 transmit idle time t idlet 0 s 9 receive idle time t idler t idlet s asymmetry t asym 1 s 10 arrival response time t arr 4.4 52 s 11 master reset time t mr 104 s 12 active pullup on time t apuot 0.5 2.0 s 13 resp onse time t resp 8.68 + ' 104 + ' s 11, 14 notes: 1. v pp - ' v prog must be within 11.5v to 12.0v. 2. applies only if a 12.0v supply is connected. if v pp and v dd are tied together, current is less than 1 p a. 3. input load is to gnd. 4. voltage difference between v dd a nd 1- w. 5. voltage difference between v pp and 1 - w. 6. 8.68 p s (115.2kbps), 52 p s (19.2kbps), 17.36 p s (57.6kbps), 104 p s (9.6kbps). 7. nominal values; tolerance = r 5%. 8. at v cc = 5.0v and 100pf load to gnd. 9. see table 7, function and speed matrix . 10. independent of baud rate . 11. minimum at 115.2kbps, maximum at 9.6kbps. 12. the master reset cycle is complete after t mr is over. 13. minimum value at overdrive speed; maximum value at standard speed. 14. ' is the time to complete the activity on the 1 - wire bus; values range from 0 (configuratio n command) up to 5130 p s (alarming presence pulse). 15. with standard and flexible speed the total capacitive load of the 1 - wire bus should not exceed 20nf, otherwise the active pullup on threshold v iapo may not be reached in the available time. with overdrive speed the capacitive load on the 1 - wire bus must not exceed 1nf. 16. baud rate calibration is valid at a static v dd operating point. post calibration changes in v dd by more than 5% may cause calibration error to exceed 5%. the ds2480b requires a 1 - wire reset command sent by the host at a data rate of 9600bps for calibration. data rates of 115200bps or higher during calibration may put the ds2480 b in an undefined state, requiring a power - down reset to restore normal operation. 17. not production tested. package i nformation for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package dra wings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 8 so s8+5 21 - 0041 maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 31
ds2480b revision date description pages changed 3/17/99 initial release ? 10/19/99 remove d preliminary status, delete d v ppmin spec, change d ? v progmax to 0.30v 29 7/1/03 changing the communication command response bit 5 to don't care status . 7 8/20/04 added references to application note 192 . clarification in the second paragraph of the device operation section . removed references to dos from the search accelerator introduction. appended to ec table note 16: the ds2480b requires a 1 - wire reset command sent by the hos t at a data rate of 9600bps for calibration. data rates of 115200bps or higher during calibration may put the ds2480 b in an undefined state, requiring a power - down reset to restore normal operation. 2 3 8 31 5/10 conversion to lead free, using ?standard? instead of ?regular? when referring to the slower 1 - wire speed, removal of load sensor (dynamic duration) as a feature, correction in figures 10, 11a, 11b (filter capacitor moved to the left of the resistor, filter resistor changed from 100 ? to 62 ? ), corr ection of minor oversights and style updates. ec table: added voltage on vpp to ground to absolute maximum ratings, deleted v pp senspr trip point, changed i weakpumax from 5.0 to 5.4 ma, changed i actpumin from 9 to 7 ma . various 31 4 /15 updated benefit s and features section 1 32 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim inte grated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the param etric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated, 160 rio robles, san jose, ca 95134 1 - 408 - 601 - 1000 ? 2015 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. maxim integrated ................................ ................................ ................................ ................................ ................................ ........................... 32

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